Weekly News | Supply chain trends in Semiconductor industry #184

184th of weekly news

01

On September 15, US GPU cloud service provider CoreWeave and Nvidia jointly announced that both sides have signed a US$6.3 billion long-term computing capacity sales agreement based on their strategic partnership agreement signed in 2023. According to the latest agreement, Nvidia will purchase any unsold capacity of CoreWeave’s global data center from the contract date to April, 2032, and promised to purchase at least 85% of its total capacity, ensuring CoreWeave’s revenue with “zero-vacancy”. The agreement covers 32 supercomputing centers planned and operated by CoreWeave. These centers have more than 250,000 Nvidia H100, H200 and next-gen Blackwell GPUs, with a peak total capacity of over 110 ExaFLOPS, three folds the total capacity of the current global Top500 supercomputing centers. Nvidia will leverage the resource pool to provide resilient training and inference services to its DGX Cloud, AI Enterprise software stack, and external LLM customers; CoreWeave will secure its long-term rental revenue, speed up building 10 green power data centers, and back-tie Nvidia's supply chain to ensure that it has the priority to gain Nvidia’s GPU compared to over other cloud vendors.

Nvidia will purchase CoreWeave’s idle capacity for the next seven years at US$6.3bn, which not only protects the flexible expansion of DGX Cloud but also raises the threshold for new cloud vendors to buy Nvidia's products. Moreover, CoreWeave’s long-term rental revenue will bring itself more capital advantages to continue floating loans to expand production, thus enlarging Nvidia’s shipments in a circular manner. After the agreement was signed, CoreWeave's stock price rose 7.4% in a single trading day, its market value exceeded US$58bn; Nvidia’s stock price also rose 2.1% after the trading hours. The Wall Street believes that the cooperation model will upgrade the AI infrastructure from “hardware sales” to “capacity financialization”, further consolidating Nvidia’s pricing rights and ecological threshold in the cloud GPU market. The deal not only secured Nvidia's computing supply chain for the next seven years but also marked the evolution of AI infrastructure from “chip sales” to “computing capacity purchase”, further consolidating Nvidia’s dominance in the cloud GPU market.

02

On September 16, MediaTek announced that it partners with TSMC to successfully develop a flagship SoC chip with TSMC’s N2P process and has completed its taping out. It is expected the mass production of the chip will start by the end of 2026. The chip is estimated to be Dimensity 9600. Based on TSMC’s new Nanosheet transistor structure, the new chip features a 1.2 fold increase in logic density, an 18% improvement in performance at the same power consumption, or a 36% reduction in power consumption at the same performance compared to the current N3E process, resulting in more efficient computing power and energy efficiency performance.

This collaboration between the two sides marks a key step of MediaTek in the advanced process field. The chip will be widely used in its flagship smart phones, edge computing and AI end devices, enabling MediaTek to compete more directly with Apple and Qualcomm in the high-end market. In addition, TSMC’s 2nm process will also serve Apple’s A20, M6 and other chips, showing that its technological maturity and customer acceptance are increasing rapidly. MediaTek pioneered taping out its 2nm chip, which not only proves its R&D capabilities but also lays a foundation for its 2026 flagship products.

MediaTek pioneered taping out its chip with TSMC’s 2nm process, and new Nanosheet transistor structure, which improves the chip energy efficiency by 36%. In other words, the AI computing of its flagship mobile phone will be raised by three folds, directly benchmarking Apple A20, Qualcomm Snapdragon 8G5, thus determining the chip type for its 2027 ultra-high end mobile phone one year earlier. By deeply binding with TSMC, MediaTek not only obtained the first batch of TSMC’s 2nm production capacity but also feeds back design-process collaboration data into the Dimensity platform, reducing Qualcomm’s bargaining space due to its reliance on Samsung technology. MediaTek’s “small chip + 3D package” solution can cut the core sizes flexibly and keep the cost of defective products within acceptable limits. Overall, the cooperation is a springboard for MediaTek to improve its technical image and market share and also an important “wind vane” for TSMC to verify its 2nm production capacity. If TSMC delivers products by the end of 2026, it will officially declare the advent of the “2nm era” of mobile chips.   

03

STMicroelectronics announced that it will invest US$60mn in building a “panel-level packaging (PLP)” advanced process test line at its Tours facilities in France, which is expected to be operational in Q3 2026. PLP technology shifts to adopt large square panels as substrate. In this way, it can process more chips simultaneously, reduce steps such as lithography, marking, and can reduce 20% material and labor costs; Combined with high automated handling and on-line inspection, the technology can keep the same yield as that of traditional wafer, and the capacity of a single production line can exceed 5 million units. The production line will first be used for producing vehicle-graded MCU, power devices, AI sensors, and other high-end products, and then extend to 2.5D/3D heterogeneous integration services, to provide European customers with a one-stop solution for local testing. STMicroelectronics has achieved PLP-based mass production at its Muar plant in Malaysia, and this time the company moved its core processes back to France to abide by the EU Chip Act, aiming to shorten the supply chain and strengthen IP protection. The project was also seen as a key step in STMicroelectronics' restructuring program so as to consolidate its competitive advantages in the automotive, industrial and IoT markets.

STMicroelectronics input US$60mn to bet on panel-level packaging, intending to use PLP to cut wafer cost by 20% and achieve daily capacity up to 5 million units. This means that it will use micro innovation in packaging to substitute upgrades of advanced process nodes which requires billions of dollars, and the capital recovery period is shortened to less than three years. As the test line will be installed in Tours, France, it can not only meet the localization requirement of the European Chips Act but also use its mass production experience in Malaysia to quickly replicate in France to form the Euro-Asian dual-wing layout. As a result, customers can enjoy the scale costs in Asia and gain the premium of European IP and supply chain security. In the short term, vehicle-grade MCU, power devices and AI sensors will be the first to be produced at the test line, thus immediately easing the anxiety of European automakers. In the long term, PLP will extend to 2.5D/3D heterogeneous integration, opening a high margin track for Chiplet, silicon photonic products, micro display for STMicroelectronics, avoiding competing with TSMC and Samsung under 7nm process. 

04

On September 18, Nvidia announced that it has agreed to buy a US$5 billion stake in Intel through private placement for US$23.28 per share to acquire 215 million shares, accounting for 4% of the company after the deal, thus becoming the fourth shareholder of Intel following the chairman of Intel, BlackRock, and Norwegian Sovereign Fund and lock a five-year strategic cooperation framework: Both sides will jointly build＜3nm CPU+GPU production lines in Arizona, Oregon and New Mexico, to insert Nvidia RTX GPU into Intel's next-gen Arrow Lake consumer processor and Xeon 6 server CPU for the first time. Through high-speed interconnections between Foveros 3D packaging and NVLink-C2C, it can achieve unified memory addressing to increase AI interference performance by 3.5 folds and reduce power consumption by 25%; At the same time, Intel will customize x86 CPU for Nvidia HGX/GB200 rack and integrate PCIe 6.0 and CXL 3.0 to advance the CPU-GPU bandwidth to 1TB per second, meeting the needs of LLM training with trillions of parameters. It is expected that both sides will mass produce the first batch of heterogeneous chips in 2026, aiming to seize 30% of the new AI server market within three years, and will jointly work together to advance edge computing, software stack, and foundry services, to reshape the new order of “x86+CUDA” in the AI era.

Nvidia’s investment of US$5bn in Intel is a strategic “collaboration” of the semiconductor landscape in the AI era. For Nvidia, its investment will bring a ticket of x86 and can extend the CUDA ecosystem from GPU to CPU, forming a threshold of “system on a chip (SoC)” while easing its reliance on advanced processes of TSMC; for Intel, the US$5bn investment in cash will support the expansion of Arizona 3nm production line and speed up activating x86 customers with AI Chiplet, providing an application scenario for IDM 2.0. In the short term, both sides will accelerate launching the CPU+GPU solution, reduce AI server system costs, and compete for the market shares of AMD and Broadcom custom chips; in the medium and long term, if the collaboration of the two sides is successful, it is expected to reshape the new standard of “x86+CUDA”, but also will face the test of architecture authorization, corporate culture integration and anti-monopoly review. Once the collaboration fails, the “Wintel”-like internal consumption will be repeated.

05

On September 18, ACM Research, Inc. announced that it has released the first high-throughput Ultra Lith™ KrF system designed to support front-end semiconductor manufacturing with KrF lithography process and has delivered to a leading logic wafer factory in Chinese mainland. The system features mature ArF platform architecture including 12 spin coaters and 12 developers (12C12D), supported by 54 hot plates capable of low, mid, and high-temperature processing, with a capacity of over 300 wafers per hour (WPH), and matches the rhythm of ACM’s mainstream KrF exposure machine. The system incorporates ACM’s proprietary backside particle removal unit (BPRV) technology and wafer-scale outlier inspection (WSOI) and enables real-time monitoring of particle and film thickness deviations during all stages of transfer, gluing, baking and development, with grain addition≤5grain@0.16μm and CD uniformity ≤ 2nm, significantly improving the yield and reducing the risk of cross contamination. Ultra Lith™ KrF supports 90-28nm logic, 3D NAND and DRAM proven processes, with key temperature control accuracy ±0.1°C, ensuring line-width consistency in development. The software platform provides multi-threaded scheduling and AI formula optimization, allowing product changeover in less than 30 minutes, with a downtime rate less than 0.5%. Therefore, it can meet the needs of wafer fab productivity.

06

During 2025 China International Fair for Trade in Services, China Mobile Xinsheng, a semiconductor and chip design company under China Mobile, officially released CM6650N, the first satellite + cell dual-mode communication IoT-NTN chip based on RISC-V, at the Digital Trade Innovation Development Fair in Xiongan New Area. The chip follows the 3GPP R17 NTN standard, with standby current less than 1 micro-A, operating frequency band at 700 MHz-2.5 GHz. It can simultaneously access high-/low-orbit satellite and ground network, to achieve global seamless voice and data link; the localization rate of the IP, EDA, manufacturing, packaging and testing of the chip is more than 90%, getting rid of reliance on Arm and foreign satellite protocol. It adopts compact package, with an area of only 8mm × 8mm, suitable for space-limited scenarios like smart watch, mobile phone, ocean-going terminal and others. China Mobile Xinsheng provides one-stop solution composed of “SIM+ Chip + Traffic”, which connects the management platform in an open manner, supports remote configuration and billing and facilitates terminal manufacturers to mass produce them for marketing rapidly. The chip fills the domestic gap of RISC-V used in the field of satellite communication and lays a foundation for building an independent IoT connecting satellites and applications on the ground. 

07

Tongfu Microelectronics announced that its CPO products have passed the preliminary reliability test. CPO technology integrates optical engine and switching chip into the same package. It can significantly reduce the length of electrical interconnect, reduce signal loss and power consumption, and is considered as the core solution of ≥800G high-speed data centers and AI computing power clusters. Tongfu Microelectronics uses mixing interconnect process with ultra-high density RDL and micro bumps, achieving 25μm optical alignment accuracy. In addition, it can keep channel insertion loss ≤ 0.5dB and error rate at the level of 1E-12 through three accelerated aging verifications including high temperature, high humidity, temperature cycle, and HAST, which can meet the reliability benchmark of Telcordia GR-468. The company simultaneously set up a one-stop platform covering optical simulation, packaging design and module testing, with mass production capacity of 8-inch/12-inch chips, and has conducted sample evaluation with several switching chip and optical module customers. In the future, it will introduce vehicle grade and edge computing scenarios. This breakthrough not only fills the domestic gap of CPO packaging & testing but also creates high-end computing market incremental space for Tongfu Microelectronics to strengthen its differentiated competitive advantages in the heterogeneous integration industry.