Weekly News | Supply chain trends in Semiconductor industry #194

194th of weekly news

01

The General Administration of Customs of China recently announced that in the first 11 months of 2025, China’s chip exports amounted to RMB1.18trn, up 38.6% YoY sharply, far higher than the chip exports last year. Among them, the chip export in November reached RMB145.6bn , a monthly record. The categories mainly include memory chips, processors, and power devices and the export destination are ASEAN, Hong Kong, and European Union, accounting for over 70% of China’s chip exports. According to industry analysis, the demand from global AI servers, new energy vehicles, and photovoltaic energy storage simultaneously drives the export of chips. Domestic production capacity of 28nm chips and larger mature process are fully released, and the price advantage has expanded; at the same time, foreign wafer fabs’ incremental projects in China have successively started mass production, and backflow chip exports go up significantly. The customs expects that the chip export over the whole year is expected to exceed RMB1.3trn, rising to be the first in a single electromechanical category for the first time.

The 38.6% growth rate not only marks a new record but also indicates that China’s chip exports transit from a “Big deficit country” to an “export engine”. Mature process + system-level packaging allows homemade chips to show advantages in terms of cost performance. Therefore, global customers support China’s chip industry with orders, and the wave of rushing for order chips will last at least to the second quarter of next year. However, behind the eye-catching data is the fact that “the price decreases although the shipment increases”- the average price of exported chips falls by 10%, and the high-end chips account for less than 15%. Once the overseas inventory rises, the price war may rapidly erode profits. If the scale advantage is changed into profit advantage, the only way is to accelerate the production of sub-14nm chips, HBM, vehicle-grade MCU and other high-end production capacity. Otherwise, the “trillions of RMB of export” will only stop as a digital carnival.

02

TSMC to expand 2nm capacity

By the end of 2025, TSMC’s plants at Baoshan, Hsinchu and Kaohsiung will have a monthly production capacity of 50,000 wafers, and their capacity will double to 100,000 wafers in 2026. At the same time, it will start its P2 plant in Arizona, USA, to increase production globally. TSMC additionally invested US$15bn in increasing original seven 2nm wafer plants to ten plants, with a target of producing 200,000 wafers per month, which is the highest speed of expanding capacity in the history of advanced process. Apple has already secured nearly 50% TSMC’s capacity for iPhone 18 series A20 chips in 2026; six major customers including Qualcomm, AMD, MediaTek, and Nvidia are queuing up to place orders, and the queue visibility has extended into 2027. The management disclosed that the price of a 2nm wafer is about US$30,000, a 50% higher than 3nm, and but it still could not stop the customers from eagerly saying “we want more”.

TSMC takes 2nm process node as a “cash printer” and expands such capacity in a wild manner. It seems that the this is driven by the demand from AI and mobile devices, but actually it is to seize the window period before 1.4nm. If TSMC’s ten plants with a capacity of 200,000 wafers per month are put into operation as scheduled, it means that TSMC secures the global supply of 2nm chips, it is difficult for Samsung and Intel to get the tickets to the arena of 2nm process node. The risk is that TSMC’s capex will soar to US$48 billion and its equipment depreciation pressure will emerge in 2026; Once the global macro-economy or terminal demand slows down, high prices of 2nm chips may force some customers to back to 3nm chips, and the decline in capacity utilization will directly impact the gross profit margin. The advanced process competition has been upgraded from a “Technology War” to an “Industrial Capacity Bet”. Now TSMC bet all its chips. The winner will take all while the loser will lose all.

03

According to report of TECHPOWERUP, Fujitsu revealed a staged roadmap for its Arm-based MONAKA series at Technology Update 2025. Its next-gen Arm server CPU is no longer just a “computing engine” but a die packaged with AI reasoning unit, achieving a fusion chip of “CPU + AI”. Fujitsu said that the new chip will be trial produced in 2027, and it will have up to 128 cores in Armv9 architecture. The chip has a built-in sparse computing accelerator, supporting FP8/INT4 mixing accuracy, and aiming to increase the target energy-efficiency to three folds as that of the current products in service. It will be used for generating AI, HPC and edging cloud. Fujitsu also opened SDK at the same time, allowing the developers to invoke AI instructions directly in the virtual address space without additional PCIe accelerators. This is seen as a response to the roadmap of “CPU+GPU” of Nvidia Grace Hopper, AMD MI300A and so forth, and it also means that the ecology of Arm servers moves from “more cores” to “more intelligent cores”.

Fujitsu has put AI power into CPU, which is ostensibly considered as a technical iteration but in essence a re-competition for industrial voice. As generative AI load shifts from training to reasoning, customers are no longer willing to additional buy a 200W accelerator to the core, because packaged AI can surpass the “plug-in” solution directly in terms of power consumption, latency, and TCO. If MONAKA can be released as scheduled, the successor of Japan’s supercomputer Fugaku would be tested first, so Arm solutions are expected to use “native AI” to break through the enterprise-class moat of x86. But the key to success is software: whether Fujitsu can make PyTorch and JAX to recognize new instructions by one click, rather than the number of cores, determines the success of the ecology.

04

With the soaring chip demand of AI data centers, Japanese Mitsubishi Electric announced to increase production capacity for optical semiconductor devices. Since January 2025, the company has mass produced the next-gen 200G PIN-PD/EML chip. A single chip supports 200 Gbps and eight chips packaged together make a 1.6T optical module; The company has started expanding clean rooms at Fukuoka and Kumamoto, planning to raise its monthly capacity from current 3 million units to 9 million units in FY2026, which is a threefold increase, a new high in the industry. The new fabs imported fully automatic indium phosphide epitaxial and backside illumination technology, improving the target yield by 15% and reducing power consumption by 20%. The management expects that the global data center optics market size will triple to US$12bn by 2029, with Mitsubishi accounting for more than half of the market. With this round of expansion, it will secure the orders from AI supercomputing, submarine cable, and edge cloud, and its order visibility has gone to 2027.

When the 800G/1.6T optical chips are deployed in scale, optical chips have become the most upstream “computational bottleneck”. Mitsubishi’s tripling its production capacity in one session will contain rivals like Coherent and Lumentum and also secure the supply chain of the next-gen GPU of tech giants like TSMC and Nvidia. If the pace of its capacity release is synchronized with the industry standards, Japan's supply chain will regain its voice in optical communications in two decades; however, if the demand curve slows down due to the macroeconomic or the early maturity of silicon optics integration solutions, its huge capex will erode its gross profit. Optical chip has shifted from a supporting role to a strategic leading role. Whoever realizes the highest yield will enjoy the pricing right of “new petroleum” in the AI era. 

05

On December 2, Xi'an ESWIN Material Technology Co., Ltd.(Xi'an ESWIN) signed an agreement with Wuhan Optics Valley Semiconductor Industry Investment Co., Ltd. to build a Wuhan silicon material base in Donghu High-tech Zone, with a total investment of about RMB12.5bn, of which the capital is RMB8.5bn, and the rest RMB4bn will be financed by bank loans. The project focuses on 12-inch advanced process single crystal polished wafers and epitaxial wafers, with planned production capacity of 500,000 units/month. After the project is completed, the company's total capacity will ascend to 1.7mn units/month or more. The products cover a wide range of chips such as logic chips, memory chips, image sensors, display drivers, etc., directly docking to needs arising from AI, vehicles, and consumer electronics. As Wuhan is a key city to develop homemade storage chips, the company has made layouts in central China and also operates its business in Yangtze River Delta, the Pearl River Delta, to consolidate its dominant position in China and speed up exporting its products.

06

On December 2, Cambricon Technologies established “Cambricon Intelligent Computing Technology (Beijing) Co., Ltd.”, with a registered capital of RMB100bn, and the new company is wholly-owned by the parent company. The operation scope of the new company clearly includes IC design, chip making and sales, indicating that the company is expanding its business from AI chips to integrated business of “design + manufacturing + sales” of chips. It intends to strengthen the control foundry of advanced process chips, Chiplet packaging and other key links, so as to lay a way for the mass production of the fourth-generation 7nm cloud edge chips.

Cambricon Technologies split its “intelligent computing” business into a separate company, which is ostensibly business divestment, but in fact is to establish more flexible finance and legal person channels for mass taping-out, stock up and customization, thus reducing business reputation risk of the parent company. Beijing Yizhuang has a 12-inch production line and complete packaging & testing resources, and the new company can dock with the local foundries and LLM customers and reduce the delivery period. However, the chipmaking process consumes huge capital, and the registration capital of RMB100mn is only enough for the first round of mask making and trial production. Subsequently, the company still need financing, and the depreciation stress will erode its profits if the capacity ramp-up cannot meet the expected level. Whether Cambricon Technologies can make a closed loop for “design-foundry-packaging & testing” by establishing the new company rather than simply releasing a new chip will determine whether Cambricon Technologies can truly turn its losses into gains.

07

On December 3, 2025, AMEC announced on the investor interaction platform that it has completed entered the “full-chain” of advanced packaging, covering etching, CVD, PVD and wafer measurement testing, and it officially released two key models: CCP high-energy plasma etcher and TSV deep silicon through-hole etcher, which can meet the requirements of HBM, Chiplet and other high-end packaging for 10 μm hole, high depth-to-width ratio and low damage at one stop. The company disclosed that the new equipment has been ordered by a lot of domestic top packaging & testing fabs. It is expected to deliver the new equipment in Q1 2026 in succession, aiming to win 30% market share of homemade advanced packaging etching equipment, and to seek verification by overseas top companies simultaneously.