来源：Future远见
近日，南京大学余林蔚团队以「Channel-bias-controlled reconfigurable silicon nanowire transistors via an asymmetric electrode contact strategy」¹为题在Chip上发表研究论文，通过非对称电极接触实现了沟道偏置控制的单栅极可重构硅纳米线晶体管。第一作者为钱文涛，通讯作者为余林蔚和王军转。Chip是全球唯一聚焦芯片类研究的综合性国际期刊，是入选了国家高起点新刊计划的「三类高质量论文」期刊之一。
场效应晶体管（Field-Effect Transistor， FET）的极性是通常静态的，由沟道中的掺杂类型决定。为了实现更多样性复杂的逻辑、增强集成电路的功能密度和细粒度，可重构晶体管由于能在运行过程中动态配置其极性从而受到越来越广泛的关注。但是基于硅纳米线的可重构晶体管需要将气液固（Vapor-Liquid-Solid，VLS）方式生长的垂直纳米线转移至平面进行制备²，难以精确定位及精准排列，无法应用于大面积电子器件，同时可重构性需要多个栅极用于有效调控能带以及肖特基势垒的厚度，增加了制备的结构复杂性。其中编程栅极需要利用高精度的光刻来精确定位硅化过程后的肖特基结³，这增加了制备工艺的难度、复杂性以及不稳定性。
南京大学的余林蔚团队提出了一种平面固液固（In-Plane Solid-Liquid-Solid，IPSLS）的生长技术，通过催化剂液滴吸收平面内的非晶硅，能够直接在平面内生长出晶态的硅纳米线⁴，同时结合多台阶的引导，能够对平面硅纳米线实现精确的定位及引导生长，并提高生长密度，整个生长过程不超过350 ℃ ⁵。基于这项技术，采用本征非晶硅和磷掺杂的N型非晶硅来获得P/N型掺杂纳米线，并利用对称电极接触。分别实现了铟掺杂P型硅纳米线的无结型FET以及磷掺杂N型硅纳米线的无结型FET，均获得了>10⁶的电流开关比，展示了IPSLS技术优异的可控互补掺杂能力，如图1所示。
图1 | 基于IPSLS的掺杂硅纳米线生长和无结型FET的制备与性能。
之后提出了一个相当简单的单栅极（Reconfigurable Field-Effect Transistors，R-FET）结构，通过使用不同的金属在S/D电极上接触自排列的掺杂硅纳米线沟道，形成不对称的接触结构。不需要任何额外的编程栅极，在单个栅极的控制下，通过简单地改变沟道偏置Vds的符号就可以改变晶体管的极性。这种相当简单的沟道偏置控制R-FET策略已经成功地在P型（图2）或N型（图3）掺杂的硅纳米线沟道上得到验证。由于S/D电极和掺杂硅纳米线存在功函数的差异，在这种结构下，一侧会形成较大但是较薄的肖特基势垒，而另一侧则会形成类欧姆接触。当在漏极（肖特基势垒较大的一侧）施加不同的沟道偏置时，a)会使初始的肖特基势垒变大但是变得更薄，此时表现为栅极控制下的隧穿型FET；b)会使初始的肖特基势垒减小但是变得更厚无法隧穿，此时则表现为栅极控制下的热电子发射型FET。通过改变沟道偏置的正负，在改变载流子输运方向的同时也改变了晶体管的极性，隧穿型模式相比较于热电子发射型模式有着相对更好的性能。在N型掺杂硅纳米线的R-FET中，展示出了> 10⁶的电流开关比以及79 mV/dec的陡峭的亚阈值摆幅（Subthreshold Swing，SS）。这种基于自排列硅纳米线和非对称电极接触的策略展示了一种相当方便和紧凑的方法来实现可重构特性，有利于提高器件及电路的集成密度，并可用于探索新一代可编程、低功耗的逻辑器件。
图2 | 基于铟掺杂P型硅纳米线沟道的可重构晶体管。
Channel-bias-controlled reconfigurable silicon nanowire transistors via an asymmetric electrode contact strategy¹
The polarity of field-effect transistors (FETs) is typically static, determined by the dopant type in the channel. To achieve more diverse and flexible logic implementation, enhance the functional density and refine granularity of integrated circuits, reconfigurable transistors (R-FETs) have gained increasing attention due to the capability of altering the N/P-type polarity of FET at runtime. However, silicon nanowires (SiNW)-based RFETs depend on transferring and re-arranging vertically SiNWs grown via the vapor-liquid-solid (VLS) method onto the substrate surface for fabrication², making it difficult to position and arrange accurately, which is unfortunately not compatible to the scalable electronic integration. Additionally, reconfiguration requires multiple gates to effectively tune the barrier profile and thickness of the Schottky barriers (SB), increasing the structural complexity for the R-FET manufacturing. The programming gates (PGs) need to be fabricated and positioned exactly over the Schottky junctions formed during the silicide process³, increasing the difficulty, uncertainty, and instability of the process.
Fig. 1 | IPSLS SiNW growth diagram and fabrication of complementary FETs.
Fig. 2 | Reconfigurable FET (R-FET) built on In-doped P-type SiNW channels.
Fig. 3 | Reconfigurable FET (R-FET) built on phosphorus-doped N-type SiNW channels.
Subsequently, we proposed a rather simple single-gate R-FET structure. The self-aligned doped SiNW channels were contacted at the S/D electrodes by using different metals to form an asymmetric contact configuration. Without the need for any additional PGs, the FET polarity can be altered by simply changing the sign of the channel bias Vds under the control of a single gate. This rather simple channel-bias-controlled R-FET strategy has been successfully testified on both the P-type (Fig. 2) or N-type (Fig. 3) doped SiNW channels. Due to the work function difference between the S/D electrodes and the doped SiNWs, a larger but thin Schottky barrier has been formed on one side, while a quasi-ohmic contact has been formed on the other side. When the different channel bias is applied to the drain (the contact with larger Schottky barrier), a) the initial Schottky barrier height increases while the thickness becomes thinner, making it behave as a tunneling mode FET under gate control; b) the initial Schottky barrier height decreases but the thickness becomes thicker which is not conducive to tunneling, thus behaving as a thermionic emission mode FET under gate control. By altering the channel bias, the polarity of the transistor is changed as well as the carrier transport direction. The tunneling mode generally exhibits better performance compared to the thermionic emission mode. The R-FET with N-type doped SiNW channels demonstrated a current on-off ratio of > 10⁶ and a steep subthreshold swing of 79 mV/dec. This strategy, based on self-aligned SiNWs and asymmetric electrode contacts, indicates a rather convenient and compact approach to implement R-FETs for enhancing the integration density of devices and circuits, and exploring a new generation of programmable, low-power logics.
参考文献
1. Qian, W., Wang, J., Xu, J. & Yu, L. Channel-bias-controlled reconfigurable silicon nanowire transistors via an asymmetric electrode contact strategy. Chip 3, 100098 (2024).
2. Heinzig, A. et al. Reconfigurable silicon nanowire transistors. Nano Lett. 12, 119-124 (2011).
3. Wind, L. et al. Nanoscale reconfigurable Si transistors: from wires to sheets and unto multi-wire channels. Adv. Electron. Mater. 10, 2300483 (2024).
4. Yu, L. W. et al. An in-plane solid-liquid-solid growth mode for self-avoiding lateral silicon nanowires. Phys. Rev. Lett. 102, 125501 (2009).
5. Wu, X. X. et al. 3D sidewall integration of ultrahigh-density silicon nanowires for stacked channel electronics. Adv. Electron. Mater. 5, 1800627 (2019).
论文链接：
https://www.sciencedirect.com/science/article/pii/S2709472324000169
作者简介
王军转，南京大学电子科学与工程学院教授、博士生导师，主要从事低维半导体器件研究，包括后摩尔硅纳米线器件集成、芯片集成光谱仪研究、Si基薄膜太阳能电池以及SiC薄膜光电性质和激光应用研究等。主持国家自然科学基金面上和青年基金，参与多项“重点研发”项目与自然科学基金重点项目。
Junzhuan Wang is a professor and doctoral supervisor at the School of Electronic Science and Engineering of Nanjing University. She is mainly engaged in the research of low-dimensional semiconductor devices, including post-Moore silicon nanowire device integration, chip-integrated spectrometer research, Si-based thin-film solar cells, and the study of SiC thin-film optoelectronic properties and laser applications. She presides over the National Natural Science Foundation and Youth Foundation, and has participated in multiple "Key Research and Development" projects and key projects of the National Natural Science Foundation.
徐骏，南京大学电子科学与工程学院教授、博士生导师。作为第二完成人获得了2003年度国家自然科学二等奖。2004年获得国家杰出青年基金，2009年入选教育部长江奖励计划特聘教授。主持和承担了多项国家及省部级科研项目。主要从事纳米与非晶半导体材料与器件物理的研究。
余林蔚，南京大学电子科学与工程学院教授，博士生导师。获国家杰出青年基金、国家海外高层次人才计划（青年项目）等项目资助。2022年，以第1完成人获教育部高等学校科学研究优秀成果“自然科学”二等奖。主持国家自然科学基金“杰出青年基金”、“后摩尔时代重大研发计划”重点项目和多项面上研究项目，承担江苏省科技支撑计划专项。主要研究方向为硅基纳米线三维生长和集成工艺、GAA-FET、柔性晶硅及显示驱动逻辑器件、硅基传感及能源应用。
Linwei Yu is a professor and doctoral supervisor at the School of Electronic Science and Engineering of Nanjing University. He has received funding from the National Outstanding Young Scientists Fund and the National Overseas High-level Talent Program (Youth Project). In 2022, he won the Second Prize of Natural Science for Excellent Scientific Research Achievements of Higher Education Institutions as the 1st completer. He has served as the principal investigator for National-Science-Fund-for-Distinguished-Young-Scholars, key projects of the "Post-Moore Era Major Research and Development Plan," and several general research projects. He also undertakes special projects of the Jiangsu Province Science and Technology Support Plan. His main research directions include the three-dimensional growth and integration process of silicon-based nanowires, GAA-FETs, flexible crystalline silicon and display driver logic devices, silicon-based sensors and energy applications.
